1. Field of the Invention
The present invention relates to the field of semiconductor packaging. More particularly, the present invention relates to a silicon interposer, semiconductor package using the same, and a fabrication method of making the same.
2. Description of the Prior Art
Integrated circuits are typically assembled into packages that are soldered to a printed circuit board. Each integrated circuit may be connected to a substrate of the package with a number of solder bumps in a process commonly referred to as controlled collapsed chip connection (C4).
2.5 D packaging and interconnect technology is a promising semiconductor packaging technology that provides costs and reliability savings over 3D packaging technology. 2.5 D packaging technology is a fast growing packaging technology which allows the integration of homogenous and non-homogenous chips on an interposer for enhanced performance and miniaturization.
FIG. 1 illustrates a conventional 2.5D IC package. In a 2.5D IC package, multiple chips 10 and 20 are mounted on an “interposer” structure 30 such as a passive silicon interposer, which is responsible for the interconnections between the chips 10 and 20, as well as the external I/Os on the package substrate 40 through the use of through silicon vias (TSVs) 32.
It is desirable to provide an improved semiconductor package and a method of fabricating the same without the need of using the package substrate.